Study of the Multiple Bit Upset Tolerant Technology Base on a Interlaced Code

As technology scales and the supply voltage decreases, memories are becoming more prone to transient errors (also called soft errors). Thus memories are the major causes of reliability problems in modern integrated circuits. Error detect and correct codes （also called error correct codes）have been well-known used to correct transient errors in SRAMs memory,a single high-energy particle affects several adjacent memory cells upsets (Single Event Multi-Bit Upset), could not be corrected by single error correcting codes,such as Single-Error-Correcting Double-Error-Detecting(SEC-DED) code. A (26, 16) interlaced code was proposed for less than two random errors correction, less than quadruple adjacent error correction (DEC-QAEC), which was composed by two systematic (13, 8) codes for correcting single errors and adjacent two errors. Theoretic analysis and simulation results show that the interlaced code is better than SED-DED code of the same length on the reliability under the equivalent memory overhead and the real-time performance. The reliability of SRAMs can be obviously improved protected against the multi-bit upset with the proposed code.