A study of the Design of Non-binary LDPC Decoder

This paper addresses decoder design for nonbinary quasicyclic LDPC(QC-LDPC) codes based on the extended min-sum (EMS) algorithm. It is necessary to perform quantities of recursive computation among the message vector, and only one single step operations is utilized to complete the check node update, which leads to larger decoder latency. In this paper, the novel non-binary LDPC decoder architecture is proposed to overcome this problem. Based on the rules of forward-backward algorithm, we utilize three single step operations to complete the check node update and optimize the check node update step operation. The hardware resource consumption for check node update increases slightly, but the cycle required is reduced to 1/3 of general decoder structure. The variable node update unit with fully parallel computation is presented without forward-backward, which removes recursive computation among the message vector and is of low complexity and latency. Moreover, an FPGA implementation for a (480,360) nonbinary QC-LDPC code decoder over GF(16) is designed to demonstrate the efficiency of the presented techniques. Simulation results show that the proposed design scheme can triple throughput of the decoder at the cost of less hardware resource consumption.