The probabilistic model for CMOS digital circuits in low supply voltage

In order to achieve the goal of low power consumption, the operating voltage is step-down, which leads to a soft error of logic devices. The probabilistic models of soft error for CMOS digital circuits with low supply voltage are proposed in this paper, and hardware circuit verification is also performed. The factors, which cause the soft error for deep submicron(DSM) CMOS logic device with low supply voltage, are introduced, and the probabilistic models for the logic gates are deduced based on the structure of devices. A novel state-transfer method is proposed to establish the probabilistic models for the digital circuit modules. In order to verify this method, we establish the hardware platform. The test results show that the probabilistic models, which obtained by the state-transfer method，match the circuits testing. Thus, proposed model can be used in the digital circuit performance study with low supply voltage.