(Conference)Design and Implementation of the connected component labeling based on FPGA

A hardware scheme for connected component labeling circuit based on FPGA is proposed in this paper. It not only meets the real-time, high accuracy requirements, but also increases a particular false alarm removing section. A pixel-by-pixel single scanning method is applied in this program, this method carries out a pixel by pixel image scanning, and while achieving the labels processing parallels in time to the parameters processing section, then according to the statistical information, removed false-alarm regions. Compared to other hardware implementation project, this scheme has its significant advantages, by optimizing labels and parameters organizing section, it is more in line with parallel processing features of hardware; time and memory consumption are reduced through removing the second scan process. Simulation results demonstrates that the total cycle of clocks for labeling a image is (M×N×2+L×4).if the image size is M×N, the maximum temporary regional labeling is L. This method is implemented on a single Virtex-Ⅱseries FPGA and has been applied to a ship detection system as a critical module.