ECG Signals Compression based on 5/3 Lifting  Wavelet and its VLSI Implementation

The wavelet transform has recently emerged as a powerful tool for many applications. However， the hardware implementation of wavelet transform is the key problem in the realtime applications. This paper presents the realization of a lifting wavelet processor for ECG data compression algorithm on a field programmable gate array (FPGA) device. This processor implements an algorithm for ECG data compression using a 5 level 5/3 integer type lifting wavelet transform. With the Altera product CYCLONE EP2C35F672C， a pipeline architecture is constructed to increase the utilization of hardware resources. The architecher take the advantages of the lifting scheme and improves the efficiency and speech of the system. The complete prototype is tested through MIT-BIH database. Experimental results showed that our algorithm not only ensured the high fidelity of signals， but also yielded good compression result. From the results， it is also confirmed that the proposed processor can execute target signal compression for the ECG signals in real time.