Optimization of parallel syndrome computation for BCH codes

Due to the increasing demand for high capacity of communications， Bose-Chaudhuri-Hochquenghem decoders with high throughput are desirable to meet higher data rate. Since the BCH codes conduct the bit-by-bit error correction， they often need a parallel implementation for high throughput application. In this paper， we propose the optimization for the parallel syndrome computation architecture. The improved architecture is proposed by simplifying the multipliers of the input. In the improved architecture， all the multipliers can be optimized， while only part of the multiplier can be optimized by the traditional methods. The experimental results show that the hardware complexity can be reduced by 67% in the design of the BCH(2040，1952) codes with parallel factor 64. In different cases of parallel factors， error correcting capability and codeword length， the improved architecture also have good performance compared with the traditional methods.