An 800Mbps Quasi-Cyclic LDPC Decoder Implementation with FPGA

In this paper, we propose an efficient highlyparallel decoder architecture for quasi-cyclic (QC) low-density paritycheck (LDPC) codes, which leads to reduction in hardware complexity. Generally, QC-LDPC codes cannot be used to design a efficient highly-parallel decoding architecture for highthroughput applications. The QC-LDPC code parity matrix structure is exploited to parallelize the row and column decoding operations. Using this architecture, we have implemented a decoder for a (8176,7154) Finite geometry-based QC-LDPC code on a Xilinx Virtex-5 LX330 FPGA, and achieved decoding throughput of 800 Mbps with 15 fixed iterations.