FPGA Implementation of High-Fidelity Radar Chaff Clutter Based on a Kinematic Model

The rapid evolution of radar systems has made electronic countermeasures a critical area of research. Among these， passive jamming remains a severe threat to radar performance. Chaff， a passive countermeasure， is widely used because of its low cost and proven effectiveness. Its core mechanism is to mimic the radar echoes of real targets， thereby deceiving or overwhelming radar signal processors. However， a major challenge in chaff research is the difficulty and high cost of obtaining comprehensive data from real-world experiments. As a result， simulation has become the primary approach for studying chaff echoes. Existing simulation methods fall into two categories： software-based and hardware-based. Software simulations can achieve high accuracy but are limited by heavy computational requirements， leading to long simulation times and high resource consumption. By contrast， conventional hardware simulations often rely on statistical approximations of chaff clouds. While faster， these methods typically fail to capture the intricate and dynamic motion of individual chaff strands， resulting in oversimplified and potentially inaccurate jamming models. To overcome these limitations， this study proposes a real-time field-programmable gate array （FPGA）-based scheme for generating radar chaff interference echoes using a motion model. The scheme fully leverages the advantages of FPGA-based pipeline processing and reconfigurable architecture by mapping complex motion model algorithms into efficient hardware logic structures. First， a hybrid modeling method integrating dynamic modeling and electromagnetic scattering theory is introduced. By calculating the radar cross-section （RCS） of each chaff filament on a per-pulse basis， the method replaces the traditional approximation based on average RCS， thereby significantly improving simulation accuracy. Second， in the FPGA implementation， a parallel processing architecture based on pulse-dimension state iteration is designed. This architecture maps the temporal evolution of chaff states， such as position and velocity， into a hardware dataflow that can be executed in a pipelined manner， enabling synchronous parallel updates of massive chaff states across multiple pulses with low control complexity. Finally， for long-sequence convolution operations， a frequency-domain segmented convolution method is proposed. This method effectively alleviates the excessive DSP resource consumption in traditional approaches and enables flexible balancing between resource usage and system latency based on signal length. To validate the correctness and effectiveness of the proposed method， statistical analysis is conducted using the Kolmogorov-Smirnov （KS） test to compare simulated results from both FPGA and MATLAB implementations with measured radar chaff interference echo distributions. The results confirm the accuracy of the proposed model and the effectiveness of the FPGA implementation.