A Low Latency LDPC Encoder for 5G

In order to meet the requirements of low-latency and flexibility coding in 5G system, an efficient HighParallelism Encoding (HPE) algorithm and the related hardware implementation for 5G Low-Density Parity-Check (LDPC) codes are proposed. The different operations corresponding to the dual-diagonal structure and diagonal structure in check matrix are processed in parallel to increase the calculation speed in HPE algorithm. To match the HPE algorithm, the Encoding Unit is designed into a multi-channel structure which can process the parallel steps in HPE simultaneously in the proposed encoder to achieve low encoding latency with acceptable hardware resources consumption. In addition, the flexible structure ensures the proposed encoder can switch among different rates over the complex channel conditions and calculate parity bits in goups to satisfy the requirement of rate matching and IR-HARQ scheme in 5G standard. With a maximum clock frequency of 200 MHZ, the implementation results into Field Programmable Gate Array (FPGA) device show that the proposed low latency LDPC encoder is capable of reaching a speed of 35 Gigabits per second (Gbps).