Abstract: For the high implementation complexity of non-binary low-density parity-check （LDPC） codes decoding algorithm， based on the simplified enhanced serial generalized bit flipping decoding algorithm （SES-GBFDA）， a method truncating the log-likelihood value for each symbol to a finite value is proposed， which can effectively reduce the memory requirement and the computational complexity， that is， truncated SES-GBFDA. For the non-binary LDPC decoder defined on the Galois Field $\mathrm{G}\mathrm{F}(\mathrm{32})$， the number of basic update units was reduced from 32 to 10 to complete the processing of variable node messages， thereby significantly reducing the computational complexity. A non-binary LDPC decoder defined over $\mathrm{G}\mathrm{F}(\mathrm{32})$ with a code length of 837 symbols and a code rate of 0.85 was implemented on the field programmable gate array （FPGA）. The results show that， the throughput of the decoder can reach 90 Mbps， compared with the decoder without log-likelihood value truncation， the implemented decoder reduces the consumption of look-up table and register resources by 64.5% and 76.3%， respectively， with 0.25 dB loss in decoding performance.