面向嵌入式部署的全尺寸卷积核渐进压缩方法

A Progressive Compression Method for Full-Size Convolutional Kernels Oriented Toward Embedded Deployment

  • 摘要: 针对视觉模型在低延迟嵌入式部署时面临的规模膨胀和任务适配性问题,提出基于张量映射和奇异值截断的全尺寸卷积核渐进压缩方法,并设计高效、通用的神经处理器(Neural Processing Unit,NPU)加速部署方案。首先,聚焦于视觉模型中负责特征提取的3×3大尺寸卷积核,通过张量映射实现轻量卷积衍生结构替代,同时重塑下游负责通道组合的1×1卷积核的能量分布;随后,基于已形成的能量衰减特性利用奇异值分解(Singular Value Decomposition,SVD)方法对1×1卷积核进行压缩,从而通过渐进压缩过程设计轻量化、部署友好的视觉模型;最后,面向嵌入式芯片普遍存在的“计算资源调度相对静态”和“NVIDIA平台量化策略难以直接迁移”的问题,提出基于队列机制的自适应动态线程调整策略和基于层级敏感度的模型混合量化策略,通过更加细粒度的任务感知动态地分配推理线程,并引入硬件可行性权重进行层级敏感度评估以实现模型混合量化,充分发挥芯片的计算潜力,确保低延迟的实时推理。测试表明,在GPU RTX 3070场景下,经全尺寸卷积核渐进压缩后,YOLOv5s、YOLOv8s、YOLOv8n和YOLOv11n的参数量压缩率分别达到2.4倍、3.9倍、1.3倍和1.5倍,推理速度较基线模型普遍提升30 FPS以上;ResNet50和MobiliNetV2在精度损失1%以内的情况下,参数量压缩率分别达到3.7倍和1.3倍,验证了方法通用性和泛化能力;经混合量化后,YOLO系列模型推理速度分别达到215 FPS、196 FPS、209 FPS和203 FPS,实现1.5~2倍推理速度的提升,参数量和内存开销等都更好地满足了嵌入式部署需求。在华为昇腾310B芯片部署场景下,尽管硬件资源受限仍可以获得高达112 FPS的实时任务处理速度。

     

    Abstract: To address the issues of the expansion of the size of computational models and their adaptability to tasks in computer vision models designed for embedded deployment with low latency, we propose a progressive compression method for full-size convolutional kernels based on tensor decomposition and singular value truncation. We further propose an efficient and general accelerated deployment scheme based on neural processing unit (NPU) devices. Firstly, a tensor decomposition technique was applied to replace the commonly used 3×3 large-sized convolutional kernels with lightweight convolutional derived structures, while the energy distribution of downstream 1×1 convolution kernels responsible for channel combination was reshaped. Secondly, leveraging the induced energy decay characteristics, singular value decomposition (SVD) was applied to perform compression on 1×1 convolution kernels to construct a lightweight and deployment-friendly vision model through a progressive compression process. Finally, in response to the common challenges faced by embedded chips-namely relatively static computational resource scheduling and the difficulty of directly migrating NVIDIA-oriented quantization strategies, we propose a queue-based adaptive dynamic thread adjustment strategy and a layer-sensitivity-aware mixed quantization strategy. Through finer-grained, task-aware dynamic allocation of inference threads and the introduction of hardware feasibility weights for layer sensitivity evaluation, mixed quantization was ultimately achieved to fully exploit chip computational potential and realize low-latency real-time inference. Experimental results showed that the parameter compression ratios of YOLOv5s, YOLOv8s, YOLOv8n, and YOLOv11n models reached 2.4×, 3.9×, 1.3×, and 1.5×, respectively, with inference speed improvements generally exceeding 30 FPS over baseline models on an RTX 3070 GPU after progressive full-size convolution kernel compression. For ResNet50 and MobileNetV2 models, parameter compression ratios of 3.7× and 1.3× were achieved with accuracy losses within 1%, which validates the generality and robustness of the proposed method. After mixed quantization, the inference speeds of the YOLO series reached 215 FPS, 196 FPS, 209 FPS, and 203 FPS, achieving speedups by a factor of 1.5 to 2, while the number of parameters and memory overhead were further reduced to better meet embedded deployment requirements. Real-time task processing speeds of up to 112 FPS were achieved in deployment on the Huawei Ascend 310B chip despite limited hardware resources. These results demonstrate that the proposed approach effectively balances compression, deployment efficiency, and real-time performance, which makes it suitable for low-latency embedded vision applications.

     

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